1. Field of the Invention
The present invention relates to a cache memory system for a data processing apparatus.
As technology advances, there is an increasing requirement for embedded processors having high processing capabilities to perform complex tasks, yet which offer a battery lifetime that is sufficiently long that it is acceptable to a user. This is particularly true of mobile processing devices such as mobile telephones, personal digital assistants, laptop computers and so on. Such mobile devices are demanding more and more processing power, but battery lifetime still remains an important concern. Thus there is a clear requirement for energy-efficient embedded processors capable of performing the computationally intensive demands of modern program applications.
2. Description of the Prior Art
It is known to provide energy efficient processors by scaling the supply voltage of the processing logic in accordance with the energy requirements of the current or recent processing workload. For example, the processing logic can be configured to operate at a plurality of different operating voltages such that both low-power efficient processing and higher-power, higher-performance processing can be performed as required. In such systems processing logic tends to have different supply voltages corresponding respectively to different target processing frequencies. Processing logic is relatively robust under supply voltage scaling and needs little adaptation in order to reliably maintain yield and function at lower operating voltages than the standard operating voltage for the logic concerned. By way of contrast memory cells are not very robust under supply voltage scaling. Thus resizing or reconfiguration of the memory cells is typically required to maintain reliable operation at low supply voltages.
It is known to provide a cache memory system in which a filter cache is employed to provide a small, low energy per access cache in between the processor and the Level 1 (L1) cache. This additional small cache then filters access to the larger, more energy-hungry, L1 cache. In these known systems the filter cache and the L1 cache have identical memory cell sizes and operating voltages and the performance benefit of the filter cache is attainable due to the smaller overall memory size (i.e. fewer memory cells) of the filter cache, which is more efficient to access provided that the hit rate of memory accesses in the filter cache is sufficiently high. However, there is a disadvantage of using a filter cache because if the memory access pattern creates a high miss rate in the filter cache then the system energy consumed can actually increase overall as a result of the requirement to access both the filter cache and the L1 cache. The processing performance can also be degraded because those cache accesses that miss in the filter cache but hit in the L1 cache necessarily take two cycles to access the required data instead of the one cycle that as it would take in a system having only an L1 cache.
It is also known to provide a cache memory system in which a “way prediction mechanism” is employed. Such way prediction mechanisms use algorithms to predict the likelihood of data corresponding to a particular required cache access being located in a particular portion of the cache and reduce energy consumption by only checking the one of the plurality of cache ways in which it is predicted that the required data is stored. In these known way prediction mechanisms, if the success rate of the way prediction falls below an acceptable level then the prediction algorithm is fine tuned in order to improve the quality of the prediction. However, the location of the data in the cache is not changed in order to improve the prediction outcome.
Thus there is a requirement to reduce the energy consumption of on-chip cache structures that does not unduly compromise the capability of the processing device to operate in a high performance mode yet enables the battery lifetime to be preserved by offering a capability of processing with a comparatively low-power consumption as and when required. Furthermore, there is a requirement to enable memory cells of a cache memory structure to operate at lower power without compromising the reliability of the memory cells.